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For Audio Equipment
MN35503
D/A Converter for Digital Audio Equipment
Overview
The MN35503 is a CMOS digital-to-analog converter designed especially for PCM digital audio equipment. It features a built-in digital filter with 16/20-bit input. It uses pulse edge modulation (PEM) and JVC advanced noise shaping (VANS) to yield the high resolution and low distortion ratio equivalent to those of 20-bit systems covering the range between 0 and 20 kHz. The chip incorporating an 8-fold oversampling digital filter that eliminates a low-pass filter after the D/A converter and greatly reduces the power consumption of the overall D/A conversion system. The chip makes a major contribution to reducing the cost and size of CD players and other digital audio equipment.
Pin Assignment
MA DIN LRCK BCK MB DVDD2 CKO DVSS2 M1 OUT1C N.C. AVDD1 OUT1D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PDO MD MC M3 DVDD1 XIN XOUT DVSS1 M2 OUT2C N.C. AVDD2 OUT2D AVSS2
Features
Built-in 8-fold oversampling digital filter using I2S bus * Bandwidth ripple: within 0.05 dB for 0 to 0.454 fs * Cutoff band attenuation (0.546 to 7.454) fs : 37dB (n-0.03125) fs to (n+0.03125) fs : min. 60dB n=1 to 7 (integer) (The above characteristics include those for an external primary low-pass filter with fs=1.95 fs.) Built-in digital de-emphasis fs=32.0 kHz 0 to14.5 kHz max. deviation +0.072dB/ - 0.047 dB fs=44.1 kHz 0 to 20 kHz max. deviation +0.077dB/ - 0.028 dB fs=48.0 kHz 0 to 21.8 kHz max. deviation +0.052dB/ - 0.053 dB (The above characteristics include those for an external primary low-pass filter with fc=1.95 fs.) The digital filter is designed to deliver the above bandwidth characteristics when used with an external primary low-pass filter with f c=1.95 fs. Built-in digital attenuation Up/down over 32 steps Support for double-speed operation (192 fs clock) 4PEM output configuration (2PEM output per channel) Support for low-voltage (3.0 volt) operation
AVSS1
(TOP VIEW) SOP028-P-0375
Choice of system clocks: 192fs , 256fs, 384fs , 512fs , 576fs Choice of input data formats: right-packed or I2S bus (16 or 20 bits, alternating channel input, MSB first) Built-in phase comparator
Applications
CD players and other digital audio equipment
MN35503
Block Diagram
For Audio Equipment
28
23
22
7
19
OSC Block DF Block * 8fs Over sampling Digital Filter * De-emphasis Filter * Attenuater 1st. Order Noise shaper Block PEM Block VANS Block
D/A Block PEM Block
I/F Block
Mode Control Block 20 25 26 27 10 13 OUT1D
2
3
4
9
1
LRCK
BCK
M1
M2
M3
MA
MB
5
MC
DIN
MD
OUT1C
16
OUT2D
OUT2C
XOUT
CKO
PDO
XIN
For Audio Equipment
Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol MA DIN LRCK BCK MB DVDD2 CKO DV SS2 M1 OUT1C N.C. AVDD1 OUT1D AV SS1 AV SS2 OUT2D AVDD2 N.C. OUT2C M2 DV SS1 XOUT XIN DVDD1 M3 MC MD PDO Function Description Operating mode selection pin 4 Serial data input pin (MSB first) LR synchronization signal input pin (fs rate) Data shift bit clock input pin Operating mode selection pin 5 Power supply pin 2 for digital circuits Clock output pin Ground pin 2 for digital circuits Operating mode selection pin 1, with pull-up resistor PEM output pin 1C (Left channel with reversed phase) No connection (Leave this pin open.) Power supply pin 1 for analog circuits PEM output pin 1D (Left channel with reversed phase) Ground pin 1 for analog circuits Ground pin 2 for analog circuits PEM output pin 2D (Right channel with reversed phase) Power supply pin 2 for analog circuits No connection (Leave this pin open.) PEM output pin 2C (Right channel with reversed phase) Operating mode selection pin 2, with pull-up resistor Ground pin 1 for digital circuits (Ground for oscillator circuit) Crystal oscillator pin
MN35503
(See Table 1.)
(See Table 1.)
(See Table 1.)
(See Table 1.)
Crystal oscillator pin (external clock input pin) (Built-in feedback resistor) Power supply pin 1 for digital circuits Operating mode selection pin 3 Reset pin/digital attenuation control pin Reset pin/digital attenuation control pin Phase comparator output pin (tristate output)*1 (for oscillation circuit) (See Table 1.) (See Table 1.) (See Table 1.)
Note*1: This pin provides tristate output indicating the result of comparing the phases of the internal f s-rate-signal and the LRCK input signal. It is at "H" level when the LRCK signal leads and is at "L" level when the signal lags. At all other times, it is in the high-impedance state.
MN35503
Operating Mode Descriptions Table 1-1. MN35503 Operating Modes
Mode Selection Pins M1 Includes pull-up resistor M2 Includes pull-up resistor M3 MA MB MC MD MODE 00 01 02 L L H L L H H L L H L L H H H L
For Audio Equipment
Pin States and Operating Modes L H H L L H L H H
MDAT MCLK MLAT L H 21 30
RSBUP RSBDN 03 10 11 12 13
RSBUP RSBDN 31 32 33
20
Serial mode
Input data form Input word length (bits) LRCK level for left channel data *1 XIN clock frequency (fs) 384 192
Right-packed 16 H *2 576 *2 384/576 *2 256/384 256
See Table 3. See Table 3. CKO output frequency (fs) DE-EMP. (fs=[kHz]) Output level VANS oversampling (fs) Theoretical signal-to-noise ratio (dB) 64 122 384 - 44.1 32 48 192 576 32 384/576 256/384 STOP - 44.1 32 0.448 x AVDD 64/96 122/138 64/96 116/132 64 116 48
See Table 3. See Table 3. - 44.1 - 0.598 x AVDD 32 95 96 138 See Table 3
Notes * 1: During 192 f s operation, the chip supports fs clock speeds up to 88.2 kHz. * 2: During 576 f s operation and 384 fs operation in modes 21 or 61, the chip supports fs clock speeds up to 32 kHz; for other modes, it supports up to 48 kHz.
For Audio Equipment
MN35503
Table 1-2. MN35503 Operating Modes
Mode Selection Pins M1 Includes pull-up resistor M2 Includes pull-up resistor M3 MA MB MC MD MODE 40 41 42 L L H L L H H L L H L L H H H L MDAT MCLK MLAT L 51 52 53 60 H 61 70 L L H L Pin States and Operating Modes H H H H H
RSBUP RSBDN 43 50
RSBUP RSBDN 71 72 73
Serial mode
Input data form Input word length (bits) LRCK level for left channel data
Right-packed 16 L *1 20 H *1 384 576
I2S to 20 L *1 384/576 *1 256/384
Right-packed 16 H Test Mode - 20
XIN clock frequency (fs)
384
576
512
See Table 3. See Table 3. CKO output frequency (fs) DE-EMP.(fs=[kHz]) Output level VANS oversampling (fs) Theoretical signal-to-noise ratio (dB) 64 122 94 138 64 122 384 -
STOP
384 STOP
384 - 44.1
576 -
384/576
256/384
512 - 44.1
See Table 3. See Table 3. 48 44.1 32 See Table 3. 0.598 x AVDD 96 138 64/96 122/138 0.448 x AVDD 64/96 116/132 64 122
Note*1: During 576 fs operation and 384 fs operation in modes 21 or 61, the chip supports fs clock speeds up to 32 kHz; for other modes, it supports up to 48 kHz.
MN35503
Serial Mode (MODE=20, 21, 60, 61)
MDAT (MA)
For Audio Equipment
D1
D2
D3
D4
D5
D6
D7
D8
MCLK (MB)
MLAT (MC)
Figure 1. Serial Mode Input Signal Timing
Table 2. Attenuation Control The 5-bit from D1 (MSB) to D5 (LSB) specifies a code of the 32 available attenuation step. (See Table 2.)
D1 0 0 0
D2 0 0 0
D3 0 0 0
D4 0 0 1
D5 0 1 0
Code 00H 01H 02H
Output Level (dB) 0.0 -1.0 -2.0
. . . . .
1 1 1 1 1 1 1 1 0 1
. . . . .
1EH 1FH
. . . . .
- 48.1 - (mute)
0=L, 1=H
Table 3. Mode Control The combination of 3-bit from pins D6 to D8 controls XIN clock frequency, de-emphasis, and reset operation. XIN Clock Frequency [fs] D6 0 0 0 0 1 1 1 1 D7 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 at MD=L 384 384 384 576 384 384 576 576 at MD=H 256 256 256 384 256 256 384 384 DE-EMP. fs=[kHz] OFF 32 OFF 32 44.1 48 OFF OFF Reset q: Reset --: Normal -- -- q -- -- -- q --
0=L, 1=H
MD=L: MODE=2 0, 6 0 MD=H: MODE=21, 6 1
For Audio Equipment
Digital attenuation and reset (Parallel mode)
MN35503
Table 4 shows how the inputs from the two pins MC (RSBUP) and MD (RSBDN) control digital attenuation except the serial modes. Table 4. Attenuation Modes Pin Name MC (RSBUP) MD (RSBDN) Mode Volume Pin States and Operating Modes L L Mute Mute (-) Normal 0dB H UP
L L Reset
H DOWN
Attenuation control
Note: The upward arrow indicates the rising edge change of the input signal; the paired arrows, the rising and falling edge changes.
There are a total of 32 attenuation levels. According to the attenuation control shown in Table-4, volume goes up or down in one step every input-signal rising-edge. Still, in the 0 dB state, up-pulse does not change the volume. Similary, in the muting state (-), downpulse does not change the volume. The change of the input signals is detected by inner clock of 16 fs period, so always use a frequency of 8 fs or less for changes in the RSBUP and RSBDN signals. Note, however, that changes in attenuation level require a period corresponding to 2 fs to complete. Do not simultaneously change the RSBUP and RSBDN signals unless setting up for a reset.
Conversion Characteristics
DV DD=5.0V, DVSS=0V, AVDD=5.0V, AVss=0V, f=16.9344MHz, Ta=25C
Analog Characteristics for 20-bit, 1 fs input Parameter Symbol Signal-to-noise ratio Dynamic range Total harmonic distortion Output level D.R. THD+N
Test Condition EIAJ (1kHz) EIAJ (1kHz) EIAJ (1kHz) 1 kHz full scale
min
typ 108 107 0.0008 2.0
max
Unit dB dB
0.0015
% Vrms
The above analog characteristics are based on measurements with the sample application circuit using mode 50 .
MN35503
Application Circuit Example
OUT R OUT L
For Audio Equipment
-12V
330
22F 0.1F
5600pF 27k
5600pF 27k
330
22F
GND
620F 0.018FG
0.1F
+12V
560F 560F 3300pFG 3300pFG
100 100
78M05
IN
100pFG
1.2kF 100pFG
+
47F
+ +
47F
+ +
OUT
100 100
56kF
47F
47F 3.3k
1.2kF
0.033F 3.3k
0.1F
560pF 3.3k 3.3k
0.033F 560pFG
3.3k 10
3.3k
AVDD
10
470F 15 AVSS2 56kF 16 OUT2D 17 AVDD2 1.5F 18 N.C. 19 OUT2C 56kF 20 M2 560 21 DVSS1 10pF 22 XOUT 1.5F 23 XIN 10pF 24 DVDD1 16.9344MHz 25 M3 26 MC 27 MD 28 PDO (TOP VIEW) 560 560 560
+
470F
AVSS1 14 56kF OUT1D 13 1.5F AVDD1 12 N.C. 11 OUT1C 10 56kF M1 9 560 DVSS2 8 1.5F CKO 7 180 DVDD2 6 MB 5 560 BCK 4 LRCK 3 DIN 2 MA 1 560 560 560
GND
56kF
+
-
620F
0.018FG
+
+
-
- +
100F
220F
+
-
M1 M2 10k 560 27 10k M3 MA MB MC MD
0.1F
DVDD
100
+
74HC14
10k MCLK UP DOWN
100k 100k 10k 0.1F
GND
0.1F
10k 100k 74HC4050 18 +5V
1.5F
1.5F
18
560 560 560
100 CKO GND
9
GND
1
DATA LRCK BCK
For Audio Equipment
Package Dimensions (Unit: mm)
SOP028-P-0375
MN35503
17.800.20 28 15 1.100.20
0.15 -0.05
+0.10
7.200.20
9.400.30
0 to 10 0.30min.
1
14 2.40max. 2.000.20
(0.65)
1.27
0.400.10
SEATING PLANE
0.100.10
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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